For repairing faulty memory cells, integrated memories, such as “DRAMs” (Dynamic Random Access Memories), generally have redundant memory cells, which are usually combined to form redundant word lines or redundant bit lines in order to be able to replace regular word lines or bit lines containing faulty memory cells on an address basis. In this case, the integrated memory is tested, for example, using an external test device or a self-test device, and then the redundant elements are programmed using “redundancy analysis.” A redundancy circuit has programmable elements, for example, in the form of programmable fuses, which are used to store the address of a line which is to be replaced.
A semiconductor memory chip is tested and then repaired after the fabrication process, for example. The addresses of those tested memory cells, which have been detected to be faulty, are stored in a “error address memory” so that, in a subsequent step, the stored addresses are used to replace these memory cells with working redundant memory cells. In this case, the memory chip is generally subject to a plurality of tests. Only those memory cells, which pass all of the tests, are deemed to be operational or working. If a memory cell does not pass one or more tests, it is deemed to be faulty and needs to be replaced with a working redundant memory cell.
From time to time, it is also normal practice, when testing the operation of memory chips, to store compressed images of the error distribution before the memory chips are repaired, in order to obtain a compressed “bit fail map.” These images of the error distribution are used to analyze a process quality in the production process for a memory chip and to detect sources of error in production. In order to obtain a compressed bit fail map, the memory's matrix-like memory cell array is generally split into address regions, which each comprise a plurality of the memory cells. For each of these address regions, for example, a bit in the bit fail map is used to store whether the memory cells within this address region are working or whether at least one of these memory cells is faulty. Such address regions are divided by word line addresses and bit line addresses, for example. The background to such a practice is that only as many test data items should be generated as are needed to be able to check and identify a process quality for the production process and any sources of error. Too high a volume of test data causes unnecessary lengthening of the test time and thus increases the evaluation time for testing the operation of a memory chip and hence the fabrication costs for said memory chip.
It has often been normal practice, to date, to obtain data for checking the process quality and sources of error in the production process when evaluating the error address memory, i.e., “fail memory”, which stores a map of the tested memory cells in the tested memory. Since such a fail memory is dependent on the size of the memory, comparatively large memories therefore have a large fail memory to be evaluated, which is associated with reading loops which are comparatively intensive in terms of test time and thus results in a long test time and evaluation time. One alternative to this would be merely to take random samples in order to keep the test time within acceptable limits.
To allow the fastest possible evaluation during testing, it is sometimes also current practice not to read the entire fail memory of the tester, but instead to provide a special smaller memory in the tester for this purpose, which undertakes this task automatically. During testing, this memory extracts a “compressed bit fail map” from the data written to the fail memory. The compressed bit fail map is obtained through prior division of the address space into address regions. This special memory has a fixed size and cannot be extended in testers today. Although the size of the memory chips fabricated today is increasing, there is no investment in new testers at the same rate. As a result, particularly, at the end of the period of use of a generation of testers, the special smaller memories are no longer sufficient for analysis. In such a case, data for checking the process quality and sources of error in the production process are instead being obtained when directly evaluating the fail memories.